AI Agents for UVM: the Next Frontier

In the last two years, the role of AI tools in developers' workflows has rapidly expanded. What were once simple "code completion" engines have since evolved into agents that can read documentation, test their own code, and improve via self-reflection. While AI has already begun enhancing RTL design workflows, its exploration in verification remains in early stages, particularly for complex tasks involving sophisticated verification methodologies. UVM, as the industry standard for hardware verification, represents one of the most challenging frontiers in this space. As various chip design companies start to integrate AI into their workflows, a natural question has emerged: Can AI generate effective UVM code?

What is UVM?

UVM is the cornerstone of modern DV. It is a SystemVerilog-based standard that combines APIs and proven guidelines to help engineers create efficient, reusable verification environments. It allows engineers to port and reuse verification components across various projects. As the architecture diagram details, UVM uses a layered, modular design: the test layer defines test scenarios, the env serves as an environment container, and the agent encapsulates interface logic. UVM also comprises components such as drivers, monitors, scoreboards, and sequencers. This standardized architecture not only reduces redundant development work but also promotes collaboration and knowledge sharing.

Challenges of AI in UVM Design Verification

The first major challenge directly comes from the limited data. Unlike software engineering tasks, where large-scale public data is abundant, the hardware domain, especially UVM verification, is severely data-limited. Open-source UVM examples are limited, and many real-world verification environments are proprietary and unavailable for training LLMs. As a result, LLMs have not had enough direct exposure to UVM code, leaving fundamental knowledge gaps. This lack of domain-specific data makes applying AI in hardware design verification much more challenging than applying AI in other data-rich fields, such as software.

The second challenge lies in complex task decomposition and systems thinking. Generating UVM code is a challenge that pushes the boundaries of even the most advanced AI tools. This task requires agents to:

• Deeply understand the UVM design philosophy. This includes the meanings and relationships between the env, agent, driver, monitor, sequence, and scoreboard.
• Usefully decompose complex testbench generation tasks into manageable sub-tasks
• Ensure consistent interoperability between modules

Each of these challenges lies on the leading edge of today's applied AI research:

• AI agents perform best with lots of high-quality training data. However, the proportion of UVM training data in modern large language models (LLMs) is exceedingly small. Therefore, existing AI tools have a strongly limited knowledge of key UVM concepts.
• With maximum context lengths, LLMs can only retain so much useful information within this "working memory." Long-horizon planning is a major challenge in the AI-for-software domain. However, the hardware domain presents even longer development cycles, demanding even stronger long-term planning capabilities.
• With integration between many verification modules, ensuring consistency across large chunks of code becomes increasingly challenging with scale.

A related critical challenge involves long context and cross-file dependency management. Production-scale hardware projects require innumerable diverse test cases. As a result, UVM-based verification code typically consists of dozens or even hundreds of files with complex macro definitions, inheritance relationships, and factory registration mechanisms. This dependency network presents a significant challenge: AI agents must have strong strategic cross-file retrieval capabilities and long-context understanding abilities. Otherwise, agents can easily introduce inconsistency defects when modifying code or extending functionality, affecting the stability and reliability of the entire verification framework.

The challenge of spec-to-coverage point mapping also presents significant difficulties. In verification tasks, accurately understanding and building the correct UVM framework is just the first step. The true marker of verification quality is not basic components such as monitors and envs; rather, it is high-quality test sequences. To develop high-quality verification code, AI agents need to fully understand everything from natural language descriptions of requirements, corresponding module design logic, and even design documents—often with hundreds of complex pages. Only with this deep understanding can they write truly valuable, high-coverage test cases. However, existing AI agents are not fully capable of mapping these complex requirements to verification IP.

Finally, the need for continuous iteration poses another major challenge. Hardware verification is never a one-time engineering effort. Experienced engineers must continuously iterate and optimize verification code based on test results. Similarly, AI agents need this capability: they must deeply understand simulation logs, coverage reports, and even complex waveform data. With these capabilities, AI agents can learn from experience, automatically refining their code based on feedback from the same tools that engineers rely on.

Opportunities of AI in UVM-based DV

UVM plays a particularly challenging role in RTL design and verification. Even the most recent hardware-focused benchmark, Nvidia's Complex Verilog Design Problems (CVDP), does not include UVM-related tasks, largely because such tasks are difficult to generate and evaluate. This gap highlights both the complexity of UVM and the significant opportunities that remain for AI to contribute in this domain.

One key opportunity lies in automated template development and quick start capabilities. AI's role in UVM design verification is limited, but still functional. Current LLMs can already generate basic UVM test frameworks. When initializing verification environments for new projects, AI agents can systematically build complete scaffolds, significantly shortening UVM testbench initialization time. By automating these highly repetitive, tedious tasks, verification engineers can focus more energy on higher-value work such as formulating advanced verification strategies and identifying corner cases.

Another promising opportunity involves iterative refinement based on feedback, operating at both the training and inference levels. At the inference level, AI agents can incorporate UVM tasks and simulation results (logs, coverage reports, waveforms) into their feedback loops to achieve real-time optimization—automatically generating new sequences when coverage is insufficient or debugging handshake logic when drivers become unstable. More fundamentally, from a model training perspective, the rich feedback signals from hardware verification environments present unprecedented opportunities to enhance AI capabilities. Recent advances in reinforcement learning for code generation in the software domain, such as SWE-RL, have shown that training code-generating language models with similarity-based rewards can effectively improve program synthesis. Reinforcement learning (RL) works by enabling models to learn optimal strategies through continuous interaction with environments and adjusting behavior based on reward signals. The hardware verification environment provides even richer and more structured feedback opportunities for this learning paradigm. Hardware verification provides immediate, quantifiable feedback through multiple concrete reward signals: functional coverage percentages, assertion pass rates, simulation convergence metrics, power and timing analysis results, and protocol compliance scores. Through Reinforcement Learning from Verification Results (RLVR), we can leverage these feedback signals to create specialized training loops. For instance, when a generated UVM testbench achieves higher functional coverage or better PPA results, the model receives positive reinforcement. Conversely, when generated code fails compilation, produces simulation errors, or yields low coverage metrics, the model learns to avoid similar patterns. This creates a powerful learning mechanism where AI systems can progressively understand the nuanced requirements of hardware verification, ultimately developing stronger capabilities in complex verification tasks through direct interaction with the verification environment's inherent feedback mechanisms.

Additionally, retrieval-augmented generation (RAG) offers significant potential to enhance reasoning and understanding. Different SoC projects share significant commonalities in UVM architecture. Through intelligent retrieval and code adaptation technologies, AI can migrate mature verification components from one project to another, efficiently performing the tedious task of reusing verification IP. In the meantime, if we can pre-parse and store structured information from design code and documents, LLMs can use RAG to produce more accurate and targeted test cases, grounded in a deeper understanding of hardware design.

Conclusion

From a modern AI agent perspective, UVM code generation is essentially a composite challenge that combines multi-stage task planning, long-context work, environment interaction, and self-verification. However, as large language models' knowledge base and reasoning capabilities continue improving, and corresponding toolchains in agent construction processes become increasingly refined and integrated, AI will rapidly become an indispensable intelligent partner in verification engineers' daily work.