ChipAgents Essentials Training

Go hands-on with agentic AI for faster RTL design, formal verification, debug and more.

Date
September 11, 2026
Time
12:00 – 2:00 PM PT
Format
In-person
Location
ChipAgents Office, Santa Clara, CA
Seats
20 seats total
Two engineers working through a flow diagram on a whiteboard

What you'll walk away with

Guided exercises and hands-on labs, with expert support throughout.

Hands-on platform experience

Work directly in the ChipAgents platform on real RTL design, verification, and debugging tasks.

Multi-agent orchestration techniques

Learn how to architect multi-agent flows for better PPA and lower token cost.

Certificate of completion

Leave with a LinkedIn-shareable certificate, plus real-time expert feedback during the session.

Who it's for

Built for engineers working at the intersection of chip design and AI-accelerated development.

Engineers

RTL design & verification engineers

Apply agentic AI directly to your existing design and verification work.

Architects

System & SoC architects

See where agentic AI fits into higher-level architecture decisions.

CAD

CAD experts

Explore tooling integration and workflow automation opportunities.

Leaders

Engineering managers

Evaluate AI-accelerated semiconductor development for your team.

Hosted by

Jonathan Thomas
Jonathan Thomas
Application Engineer
Gayatri Sridhar
Gayatri Sridhar
Application Engineer

Questions

Is there a cost to attend?

No. This session is complimentary, and light refreshments are provided.

Do I need to be approved to attend?

Yes. Registration is subject to host approval. You'll be notified once your registration is reviewed.

Will I receive proof of completion?

Yes. Attendees receive a LinkedIn-shareable Certificate of Completion after the session.

Where is it held?

At the ChipAgents office in Santa Clara, CA. The exact address is shared once your registration is approved.

Seats are limited to 20

Registration is subject to host approval.

Save your spot now ↗