Building Multi-Agent Systems for ASIC Flows

Semiconductor Engineering discussion on building multi-agent AI systems for ASIC design flows.

Limitations on Transistor Scaling and the Memory Wall

A look at the physical limits of transistor scaling and the growing memory wall challenge.

AI's Impact on Next-Gen Engineers

DAC 2026 · Kexun Zhang (ChipAgents)

Explore Vibe Coding, Agentic Management, and the Future of Next-Gen Engineers in this in-depth talk by ChipAgents Head of Research.

Renoir: ChipAgents' First Model

DAC 2026 · Tanay Biradar (ChipAgents)

The step-by-step guide to ChipAgents first Model: Renoir.

AI Agent-Driven Timing Closure

DAC 2026 · Dakota Barnes & Nik Belle (ChipAgents)

Use loops to understand how AI Agents can be applied to solve one of the industry's biggest bottlenecks: Timing Closure.

AI-powered Root Cause Analysis for Advanced Silicon Design

DAC 2026 · Zackary Glazewski (ChipAgents)

ChipAgents Founding AI Engineer walks you through Hardware debugging using ChipAgents RCA: the first autonomous, agentic AI system for end-to-end ASIC root cause analysis.

AI-Native Chip Design: From Physics to Silicon

DAC 2026 · Karthik Chandrasekaran (NVIDIA)

How closed-loop, autonomous engineering systems reason across specs, RTL, and verification context to take chip design from physics to silicon end to end.

Formal Verification for Scalable IP and SoC Design in the Era of AI

DAC 2026 · David Vincenzoni (STMicroelectronics)

First-silicon success demands 100% functional verification and code coverage. Coverage-driven UVM gets you there, but it's demanding, slow to learn, and hard to debug. How formal verification, amplified by AI, scales IP and SoC verification instead.

FPGA-Based Prototyping Today and Tomorrow with AI

DAC 2026 · Stefano Cumia (STMicroelectronics)

Inside ST's FPGA prototyping flow for pre- and post-silicon validation, with Python-automated lab testing, and where AI can take it next: automatically mapping RTL to FPGA resources and generating lightweight test benches that reproduce lab behavior for fast debug.

AI-Accelerated Chip Design Workflows on AWS

DAC 2026 · Jhen-Wei Huang (AWS)

How AWS tackles the time, compute, and talent bottlenecks of semiconductor design with secure, scalable EDA infrastructure and domain-expert AI agents deployed inside private VPCs, including a customer that cut design cycles from 30 to 18 months.

Agentic AI in Chip Design

How agentic AI is transforming chip design and verification workflows.