IC-star overview

Powering digital and analog designs

Physical AI demands more from silicon as process technology advances toward subnanometer nodes and designs span multiple heterogeneous dies. Each node migration adds constraints, while rising test costs and tighter schedules stretch engineering capacity.

Engineers still hand work between dozens of disconnected tools, and each handoff loses context and adds days of iteration. IC-star preserves design intent, co-optimizes models, harness and tools, and executes toward verified outcomes.

1. IC-star in a nutshell

IC-star is ChipAgents’ chip neural engine for AI-native digital and analog design. It connects organizational knowledge, agentic reasoning and physical prediction within a closed execution loop.

Security-first: installed, trained and run inside your firewall. Context, results and constraints stay in one system, so nothing is lost between RTL, verification and implementation.

1.1 IC-star reasoning core

Concurrent multi-objective co-optimization throughout design flows

The reasoning core performs task decomposition, dependency-aware planning and agentic orchestration across design workflows. It directs specialized solution agents, physics-aware models and the ontology database, using engineering results to evaluate constraints and revise execution plans. Scenario-specific reflection analyzes execution traces, verification results and engineering metrics to identify failure causes and unnecessary iterations. It then refines its own components, including system prompts, agent instructions, tool descriptions and EDA knowledge.

In digital design, this couples RTL generation and verification with timing and power optimization. In analog design, it coordinates parameter exploration and simulation-driven optimization against circuit performance constraints.

1.2 Physics-aware models

Early physical estimates for agentic iteration

Neural surrogate models estimate timing, power, DRC violation risk and placement-and-routing outcomes before full implementation, with prediction error below 10%. These predictions help the reasoning core prioritize candidates, identify likely constraint violations and allocate simulation and implementation resources.

For digital workflows, physical estimates guide RTL and implementation exploration. For analog workflows, surrogate feedback guides candidate selection during circuit optimization. Simulation, verification and implementation tools validate selected candidates; surrogate predictions inform exploration but do not establish signoff correctness.

1.3 IC design ontology

A shared context layer for organizational design knowledge

IC design ontology encodes design data, IP, specifications, constraints and engineering know-how to ground agent reasoning in customer-specific context. Authorized engineers and agents can access proprietary design data and IP securely. Agents build on the ontology to refine planning and optimization, capturing engineering expertise in reusable context and workflow recipes.

1.4 Design-driven model navigator

Design-driven model routing and inference coordination

The design-driven model navigator selects language models according to task complexity, quality requirements, latency, inference cost and deployment constraints. It coordinates model selection with the agent harness and inference infrastructure. It can swap models mid-task, co-optimizing with the harness and KV-cache for the best time to results.

2. The IC-star advantage

IC-star supports both digital and analog workflows. Digital capabilities include RTL design, verification, debug, coverage closure and PPA-aware optimization, while analog capabilities include schematic design, behavioral modeling, simulation, layout generation and physical verification. Four capabilities set the platform apart.